1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a nonvolatile memory device and method of manufacturing the same which simultaneously forms a selection gate and an erase gate, and reduces a cell size.
2. Background of the Related Art
Generally, a nonvolatile memory device maintains information stored in a cell even in case of power being turned off. Examples of the nonvolatile memory device include Mask ROMs, PROMs, EPROMs, EEPROMs and Flash memory.
Particularly, there are two types of the Flash memory, an NOR type and a NAND type. A certain number of source/drains are shared by buried N+(BN+) lines in the NOR type Flash memory, while a source in one cell and a drain in a next cell are shared in the NAND type Flash memory.
Meanwhile, in the nonvolatile memory device, to xe2x80x9cerasexe2x80x9d memory data refers to an action of discharging electrons in a floating gate, and to xe2x80x9cprogramxe2x80x9d, on the other hand, refers to an action of injecting electrons to the floating gate. Additionally, a gate constructed as an erase gate, by making erasing functions of a control gate independent, is referred to as a split gate.
A related art nonvolatile memory device and method of manufacturing the same will be explained with reference to the accompanying drawings.
FIG. 1 shows a structure of a related art nonvolatile memory device. As shown in FIG. 1, the related art nonvolatile memory device has a split gate structure including a floating gate 15, a control gate 17 and an erase gate 20.
FIGS. 2a to 2d show process steps of a related art nonvolatile memory device. As shown in FIG. 2a, a gate oxide film 12 is formed on a surface of a semiconductor substrate 11, and a first CVD oxide film 13 is in turn formed on the gate oxide film 12. The first CVD oxide film 13 is then selectively etched using a buried N+ mask. In this process, the gate oxide film 12 is used as a tunnel oxide film during program.
Subsequently, a first sidewall 14 is formed in contact with both sides of the first CVD oxide film 13 by depositing an insulating film on the first CVD oxide film 13 and performing etch-back to the entire surface. A buried layer of high density (not shown) is then formed on the surface of the semiconductor substrate 11 at both sides of the sidewall 14 by ion implantation using the buried N+ mask.
As shown in FIG. 2b, a first polysilicon is formed on the surface of the gate oxide film 12 including the sidewall 14 and the first CVD oxide film 13. Then, a floating gate 15 is formed by selectively etching the first polysilicon. Subsequently, an inter poly oxide film 16 is deposited on the floating gate 15.
As shown in FIG. 2c, a control gate 17 including a gate cap insulating film 18 is formed by depositing and selectively etching a second polysilicon and a second CVD oxide film on the inter poly oxide film 16.
As shown in FIG. 2d, a second sidewall 19 is formed in contact with both sides of the control gate 17 by depositing an insulating film on the control gate 17 and performing etch-back. An erase gate 20 is then formed by depositing and selectively etching a third polysilicon on the entire surface including the second sidewall 19.
In the aforementioned nonvolatile memory device, programming operation is performed when hot electrons are implanted to the floating gate, and erasing operation is then performed when electrons of the floating gate are moved to the erase gate.
However, the related art nonvolatile memory device and method of manufacturing it has several problems.
First, since a hot hole generated by band to band tunneling during the erase action is trapped in a tunnel oxide film, leakage current between the control gate and the semiconductor substrate is increased.
Moreover, since each gate forming process is proceeded without being aligned and the erase gate is formed independently, the size of the memory device increases.
Accordingly, the present invention is directed to a nonvolatile memory device and method of manufacturing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile memory device and method of manufacturing the same simultaneously forming a selection gate and an erase gate, and reducing the cell size.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.
In another aspect, the method of manufacturing the nonvolatile memory device according to the present invention includes the steps of: layering a first insulating film, a first conductive layer, a second insulating film and a second conductive layer; forming an erase gate having the second conductive layer and a selection gate having the first conductive layer in a first direction by patterning the second conductive layer, the second insulating film, the second conductive layer and the first insulating film; forming a third insulating film on the entire surface including the selection and erase gate and etching back the third insulating film to form sidewall in contact with both sides of the layered selection gate and erase gate; forming a fourth insulating film on an upper surface and an edge of the erase gate; forming a floating gate overlapping the erase gate at a certain width by forming and patterning a third conductive layer on the fourth insulating film; forming a fifth insulating film on the floating gate; forming a source/drain region in a surface of the semiconductor substrate using the floating gate and the erase gate including the sidewalls as masks; and forming a fourth conductive layer on the entire surface including the floating gate and the erase-gate and patterning the fourth conductive layer to form a control gate in a second direction perpendicular to the gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.